Multiple memory units such as Dynamic Random Access Memory units (DRAMs) and logic units, such as Application Specific Integrated Circuits (ASICs) and Microprocessors, utilized in computers for the storage and retrieval of data computations and etc., in conjunction with driver circuits, are generally provided in integrated circuit packages, or computer memory or logic modules. In these integrated circuit packages, leakage currents are a well known problem, and a major source of such leakage currents are the driver circuits. Conventionally, a large numbers of field effect transistors (FETs) are utilized as drivers, and while the leakage of any single driver transistor is generally rather small, the overall leakage of the circuit package is usually quite extensive due to the number of drivers employed.
In conventional driver circuits of the prior art, the system ground is applied to the gates of inactive transistors. The gate to source voltage (Vgs) of these transistors remains at or slightly above ground. The channel lengths of the FET transistors are chosen to be long enough to avoid unwanted leakage current. Generally, the accumulative leakage current requires construction of driver devices having minimum leakage, and the latter, in turn, places severe limitations on chip design, especially slower performance and greater chip area requirements.
An arrangement for reducing driver leakage in off chip driver circuits is described in U.S. Pat. No. 5,257,238, issued to Ruojia Lee et al on Oct. 26, 1993, wherein the leakage in the driver circuit is reduced by applying a negative bias, rather than simply ground voltage, to the inactive driver transistors. Now, while this arrangement results in a more complete turn off of the inactive transistors, and thus a reduction in leakage, it requires considerably more time to bring the negatively biased transistors up to an active state. Consequently, the speed of this prior art arrangement suffers accordingly.